Recently, the Quantum Interface Devices and Systems research team at the Beijing Academy of Quantum Information Sciences (BAQIS), in collaboration with researchers from the School of Integrated Circuits at Tsinghua University and the School of Integrated Circuits at Shanghai Jiao Tong University, has made important progress in high-performance quantum control-and-readout integrated circuits for scalable quantum computing.

Guided by the vision of “Quantum–AI Integration,” the team introduced, for the first time, a neural-network-based adaptive on-chip learning mechanism into a cryogenic qubit readout chip. This approach enables dynamic adaptation of qubit readout thresholds, as well as real-time monitoring and adaptive calibration of readout-parameter drift. Based on this innovation, the team successfully developed the first AI-enhanced cryo-CMOS quantum control-and-readout chip.

The work, entitled “A Cryo-CMOS Fully-Integrated Superconducting Qubit Reflectometry Readout IC with FCNN-Based Adaptive Drift Mitigation and FIR-DSM-Based Stimulus TX,” was presented at the 2026 IEEE Symposium on VLSI Technology and Circuits, a premier international conference in the field of integrated circuits, held in the United States from June 14 to 18, 2026.

Advancing the scalability and system-level integration of quantum computing is essential for accelerating its practical deployment. Cryogenic quantum control-and-readout chips, which operate at cryogenic temperatures in close proximity to quantum processors, are widely regarded as a key enabling technology for large-scale quantum computers. Since 2021, the team has systematically advanced cryogenic integrated-circuit research across the full technology chain, spanning “device modeling — core IP development — control-and-readout chip design — platform-level validation.”

As the research progressed, qubit readout chips have encountered a series of critical challenges, including noise limitations, fidelity degradation, the trade-off between limited cryogenic cooling power and high-performance control, and random parameter drift during long-duration operation. The coupling among these factors further increases the difficulty of designing high-performance and highly stable quantum control-and-readout chips.

To address these challenges, the team proposed an AI-enabled cryo-CMOS quantum control-and-readout chip architecture. The chip integrates a quantum-state classifier based on a fully connected neural network (FCNN), which performs on-chip learning and weight updates to optimize quantum-state discrimination thresholds in real time. It also implements real-time drift monitoring and adaptive calibration of readout parameters, using gradient-based algorithms to dynamically compensate for qubit readout-parameter drift.

Compared with conventional approaches that rely on periodic manual calibration, this architecture provides an effective solution for mitigating drift during long-duration operation. It also offers the potential to support adaptive qubit initialization, thereby providing an important hardware foundation for the long-term stable operation of future large-scale quantum computing systems.

In terms of circuit design, the team developed a low-power stimulus-generation technique based on an embedded finite impulse response filter and delta-sigma modulator (FIR-DSM), together with a digital-IF reflectometry readout circuit topology. The chip achieves full integration of key readout functions, including readout-stimulus generation, reflected-signal reception, digital demodulation, quantum-state classification, and drift calibration.

Fabricated in a 28 nm CMOS process, the chip’s stimulus transmitter consumes only 2.6 mW at 4 K, approximately 1.9 times lower than previously reported comparable designs. The total power consumption of the readout chip is only 10.3 mW, representing the best reported level to date among cryogenic qubit readout chips with comparable integration.

Figure 1. The AI-enhanced cryo-CMOS quantum readout chip and measurement setup

The main contributors to this work include Associate Professor/Adjunct Researcher Tiefu Li of BAQIS/Tsinghua University, and Senior Engineer Qichun Liu of BAQIS; Associate Professor Yanshu Guo of Shanghai Jiao Tong University; Professor Hanjun Jiang, Researcher Ning Deng, and Professor Zhihua Wang of Tsinghua University, together with graduate students Heyue Li, Siqi Zhang, Jun Shi, and Shijie Yin; and Professor Yuanjin Zheng of Nanyang Technological University, Singapore. This work was supported by the National Natural Science Foundation of China and the National Key Research and Development Program of China.

The IEEE Symposium on VLSI Technology and Circuits is one of the most influential flagship conferences in the international integrated-circuits community. Jointly organized by IEEE and the Japan Society of Applied Physics, the symposium covers cutting-edge topics in advanced semiconductor process technology, integrated-circuit design, and system implementation. It serves as a major international platform for presenting the latest research achievements in integrated circuits worldwide. Together with ISSCC and IEDM, the VLSI Symposium is widely recognized as one of the three most influential top-tier conferences in the field, attracting leading researchers and industry experts from around the world every year.

Link:
https://vlsi26.mapyourshow.com/8_0/sessions/session-details.cfm?scheduleid=199