Researchers at the Beijing Academy of Quantum Information Sciences (BAQIS) have developed a dedicated control processor designed for real-time quantum error correction. The processor supports updates to future instructions and operation parameters during program execution while maintaining deterministic timing, addressing the need for both dynamic changes to control operations and precisely timed execution in applications such as real-time quantum error correction. The findings were published in Review of Scientific Instruments on October 23, 2026, under the title “Time-deterministic and instruction-dynamic execution: A field-programmable gate array quantum-control processor.”

Quantum error correction requires repeated measurements that provide information about errors, classical processing of that information, and adjustments to subsequent operations when needed. As quantum computations grow in scale and run for longer periods, control systems must continue to receive new instructions while ensuring that each operation follows precise timing requirements. Integrating real-time feedback into an ongoing control process is a challenge that classical electronics must address on the path toward fault-tolerant quantum computing.

The team proposed the Time-Deterministic and Instruction-Dynamic Execution (TIDE) architecture, which separately manages future plans that can still be revised and operations that have already been committed. Instructions for subsequent operations can be added or modified while a program is running, and operation parameters can be adjusted in response to new information. Once an operation’s content and execution time have been finalized and committed, they are protected from subsequent changes, and independent hardware handles its timed execution. This allows the control system to carry out committed operations while receiving and scheduling new control decisions (Figure 1).

Figure 1. Schematic of TIDE’s role in a quantum control system.

The researchers used a field-programmable gate array (FPGA) as a validation platform, testing the processor’s design and key functions with reconfigurable hardware circuits. The tests confirmed that parameters could be adjusted and instructions replaced or added while a program was running. Under the specified scheduling and output conditions, committed control instructions were issued at their scheduled times, with their timing and content unaffected by subsequent updates. These results show that dynamic updates and precise timing can be coordinated within a single processor (Figure 2).

Figure 2. Hardware test results for instruction updates during program execution.

For real-time quantum error correction, these capabilities provide a means of translating decisions from classical processing into subsequent quantum operations. The same approach also applies to quantum algorithms in which measurement outcomes determine later computational steps, and to adaptive calibration that adjusts parameters as experimental conditions change.

Looking ahead, this architecture, already validated in hardware, could be developed into a dedicated quantum-control chip. Chip design tailored to quantum computing could improve integration, optimize power consumption, and strengthen coordinated control across multiple channels. Further integration with qubit readout, analysis of error information, and generation of control signals could provide the hardware support needed for real-time quantum error correction and long-running fault-tolerant quantum computation.

The paper’s first author is Xiaoqin Luo, an engineer at BAQIS, and its corresponding author is Xiaolu Su, an assistant researcher at BAQIS. Jiayun Song, a visiting student at Tsinghua University, is also a coauthor. The authors thank Professor Li You of Tsinghua University, who also holds an adjunct appointment at BAQIS, for his support and encouragement. This work was supported by the National Natural Science Foundation of China.

Article link:https://doi.org/10.1063/5.0356629