Time：July 9 2021, 14:00-15:30

Venue: Room 526

Tencent Meeting ID: 142632550

Password：0709

Title：Cryogenic electronics for scaling up semiconductor spin based quantum circuit

Host：Tian Pei, Associate Research Scientist, BAQIS

Abstract：

In this talk, I will briefly review the key interconnection ideas and tools that underpin scaling up classic electronic circuit, contributing to the exponential progress in computational power as described by Moore’s law. Currently, the quantum counterparts are still absent and yet to be developed, significantly slowing down the prototype-test-feedback development cycle. I will present two cryogenic interconnection solutions based on my research, which hopefully can fill some of the gap. The off-chip interconnection solution I developed can supply up to ~1000 interconnects and can be flexibly reconfigured to meet different wiring requirement. To go beyond 103 interconnects toward 106 interconnects, I will present an on-chip solution based on parallel refreshed charge-locking array. I personally believe integrated charge-locking circuitry to provide individual tuneability is a more achievable path to scale up as compared with those relying on unprecedented device uniformity. A key open question remains to be answered for charge-locking circuitry is the possibility of implementing lowest-level signal multiplexing circuitry at mK instead of higher temperature. If it is possible, the wiring overhead to supply ~106 interconnects at mK can largely be relaxed. For performance evaluation, I will present detailed power dissipation analysis for conventional serially refreshed charge-locking array, showing its super-linear growth of power dissipation with size (quadratic for 1D addressing and to the power 3/2 for 2D addressing). In contrast, the parallel refreshed charge-locking array show close to linear growth with size, being much more scalable. I will also benchmark the power dissipation of both serial and parallel approaches, assessing the its compatibility with the cooling power of a typical crystat available at 100mK. Along presenting those two interconnection solutions, alternative solutions and attempts will also be discussed.

About the Speaker：

Dr Xinya Bian, I obtained my bachelor’s degree in electrical engineering from University of Liverpool in 2011. In the same year, I started my PhD research at the centre for advanced photonics and electronics (CAPE), University of Cambridge. The research group focuses on studying the feasibility of coherently manipulating single trapped charge inside dielectric defects which inherently exist in many. The study is with the ultimate aim to address the ‘scalability’ issue related to QD type device. I am personally responsible for the single charge readout device based on RF reflectometry. After obtaining my PhD degree, I started my post-doctor research in Materials Department, University of Oxford in 2016. My research interests include cryogenic electronics for scaling up quantum circuit, quantum charge transport at single molecule level, as well as solid state nanopore based DNA sequencing. For the 1stresearch topic, I focus on developing cryogenic interconnection solutions with the aim to overcome IO bottleneck for device batch testing and quantum circuit prototyping.